Prime Highlights
- Intel has begun using ASML’s High NA EUV machines to produce select layers of its Panther Lake chips, following experiments that began in 2024.
- The High NA tool costs around $400 million, twice the price of a standard EUV machine, and remains technically challenging to deploy.
Key Facts
- ASML is a Dutch company that makes lithography machines used to print circuit patterns onto microchips.
- Intel manufactures Panther Lake chips using its 18A process and standard EUV machines, alongside the newly adopted High NA tool.
Background
Intel Corp. has decided to use a high-end machine from ASML to manufacture some of its flagship Panther Lake laptop chips, ASML said on Tuesday, a move that will help the chipmaker learn to use the tool more effectively.
Following experiments that began in 2024, Intel has started using ASML’s next-generation high numerical aperture (High NA) extreme ultraviolet (EUV) machines to help produce a portion of its Panther Lake processors, according to ASML. These machines print circuit patterns onto microchips.
The industry has long debated when it makes economic sense to begin deploying High NA tools, which chipmakers are likely to need in future as they continue shrinking the atomic-sized features that make up chips.
The High NA equipment costs around $400 million, roughly twice the price of a standard EUV machine, and remains technically challenging to introduce into production processes.
Intel is deploying the High NA tool for specific layers of the chip, a step that will help both Intel and ASML gather data and optimise the equipment further. Intel declined to comment on the announcement.
The company uses its 18A manufacturing process to fabricate Panther Lake chips and already relies on ASML’s standard EUV lithography machines for the process. Lithography refers to the use of light to draw the complex patterns that form the circuits on a chip.
The development marks a step forward in the adoption of next-generation chipmaking tools, as manufacturers weigh the cost and complexity of upgrading equipment against the need to keep pace with shrinking chip features.
